FIGS. 1 to 5 are sectional views illustrating a capacitor of a semiconductor device and a method of manufacturing the same. As illustrated in FIG. 1, first polysilicon layer 120 may be formed over semiconductor substrate 100 and insulating layer 110. Insulating layer 110 may be a gate insulating layer. First polysilicon layer 120 may be a gate conductive layer.
As illustrated in FIG. 2, first photoresist layer pattern 130 may be formed over first polysilicon layer 120. First photoresist layer 130 may partially expose the surface of first polysilicon layer 120. A TEOS oxide layer may be arranged between first polysilicon layer 120 and first photoresist layer pattern 130. A TEOS oxide layer may be a capping insulating layer. DA ion implantation may be performed into an exposed portion of first polysilicon layer 120. After DA ion implantation, first photoresist layer pattern 130 may be removed.
As illustrated in FIG. 3, capacitor dielectric layer 140 may be formed over first polysilicon layer 120. Capacitor dielectric layer 140 may have an Oxide-Nitride-Oxide (ONO) structure. Capacitor dielectric layer 140 may comprise lower oxide layer 141, nitride layer 142, and upper oxide layer 143. Second polysilicon layer 150 may be formed over capacitor dielectric layer 140.
As illustrated in FIG. 4, second photoresist layer pattern 160 may be formed over second polysilicon layer 150. Second polysilicon layer 150 may be etched using second photoresist layer pattern 160 as an etching mask to form second polysilicon layer pattern 155. Capacitor dielectric layer 140 may be etched using second photoresist layer pattern 160 as an etching mask to form capacitor dielectric layer pattern 145. After forming second polysilicon layer pattern 155 and/or capacitor dielectric layer pattern 145, second photoresist layer pattern 160 may be removed.
As illustrated in FIG. 5, insulating layer 170 may be formed over semiconductor substrate 100. First metal contact 181 and/or second metal contact 182 may be formed in insulating layer 170. First metal contact 181 may connect to second polysilicon layer pattern 155. Second metal contact 182 may connect to first polysilicon layer 120. Upper metal wiring line layer 191 may be formed over first metal contact 181. Lower metal wiring line layer 192 may be formed over second metal contact 182.
A capacitor having a polysilicon-dielectric layer-polysilicon structure (e.g. PIP structure) may include first polysilicon layer 120 as a lower electrode and second polysilicon layer pattern 155 as an upper electrode. When forming a capacitor, a doped polysilicon layer may need to be deposited and etched, which may make a manufacturing process relatively complicated. Complications may be caused by particles, which may make it difficult to control processes.